1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to memory devices and junction field-effect transistor (JFET) device structures.
2. Description of the Related Art
Dynamic random access memory (DRAM) is one class of memory conventionally implemented in electronic devices. DRAM memory cells typically include an access device and a memory element. The access devices allow the transfer of charges to and from the memory elements to facilitate read and write operations in the memory device. Complementary metallic oxide semiconductor field effect transistors, commonly referred to as “CMOS” transistors, are typically used as access devices for the DRAM memory cells. The memory cells are typically arranged in a number of rows and columns to provide a memory array.
DRAM devices are dynamic because once a bit of data is written into a memory cell, the data begins to degrade. Specifically, electrical energy stored in the memory element of a DRAM memory cell may only be representative of the data for a finite period of time before the electrical energy increases or decreases and no longer represents the original data. To avoid loss of data, the memory cells are continuously refreshed or re-written. Retention time of a memory cell refers to the length of time that a memory cell is able to maintain memory before it needs to be refreshed. Typically, the retention time for requirement DRAM memory cells is 64 ms and, as such, cells are refreshed every 64 ms. If a memory cell in the memory array has a retention time less than 64 ms, the system may crash and data may be lost as bits become unreadable from the memory array. Various factors may contribute to a particular cell being unable to achieve a retention time of 64 ms.
Leakage is one possible cause of a reduced retention time. Leakage refers to a condition where electrical current flows when no current flow is expected, such as when a device is in an off state. For example, in a memory cell, leakage may refer to current flowing in and/or out of a memory elements when the access device is off. One cause of leakage in CMOS access devices are trap states. Trap states may occur when dangling bonds are created at the interface of silicon and silicon dioxide. As a result of the dangling bonds, electrons and holes may be created and recombined (generation and recombination centers) and may, therefore, prevent transistors from completely turning off. FIG. 1 illustrates a conventional nMOS-based DRAM cell exhibiting state or bit fluctuations at 100 degrees Celsius and 150 degrees Celsius. The state fluctuations may also result in unpredictable retention times. The erratic nature of the fluctuations result from electrons trapped along the interfaces between semiconductor and insulator (oxide), such as the gate oxide in CMOS access devices that has a gate oxide interface with the semiconductor channel.
In addition to leakage, CMOS access devices exhibit a high gate capacitance. This results from the gate oxide separating the gate from the channel. Gate capacitance is related to voltage, current and the speed of the access device by the following formula: (C×V)/I=t; where C represents gate capacitance, V represents voltage, I represents current, and t represents time. Thus, assuming a constant voltage supply, as the current decreases or as the capacitance increases, the speed of the device slows. A higher supply voltage (Vcc) helps to offset the effects of the gate capacitance and maintain a reasonable speed for the access device.
Generally, the on chip power supply of DRAM memory arrays provides greater than 1.5 V Vcc. In addition to maintaining the operational speed of the access devices, a higher Vcc may result in decreased bit failures in a conventional nMOS-based DRAM cell. FIG. 2 is a scaled plot illustrating decreased bit failures in a memory array as a function of time and as a result of higher Vcc in a conventional nMOS-based DRAM memory cell. Thus, a higher Vcc provides for a higher drive current which, in turn, results in a better ability of the access device to write into the memory element. Thus, to provide fast nMOS access devices, Vcc voltages should be relatively high, i.e., greater than 1.5 V.
Because of the higher voltages required for operation of CMOS access devices, scaling of the CMOS devices may be problematic. Specifically, as the devices are scaled there may be an increase in parasitic effects between memory cells, as well as between the memory cells with other components. Additionally, as memory cells are scaled to provide for smaller and more densely packed arrays, leakage by the CMOS access devices increases. Furthermore, while it may be generally preferable to use a higher supply voltage in many applications the higher supply voltage results in higher power consumption. Embodiments of the present invention may address one or more of the issues set forth above.